The interface between a connectionless data-based network and a clocked telephone system typically requires the use of buffers to handle variable delays between transmission of cells on the network side. Traditionally, the function of buffering for delays in the receipt of cells on the network side, and the function of buffering for re-assembly of data from the cells, to be passed to the telephone network, has been implemented in a single buffer entity. For example, in certain Asynchronous Transfer Mode (ATM) Adaptation Layer One (AAL1) Segmentation and Re-assembly (SAR) engines, the single buffer is typically organized around a frame of DS0 time slots. This requires the use of relatively expensive static or dynamic random access memory (SRAM or DRAM).
Accordingly, there is a need identified in the prior art for an apparatus and method that can implement the segmentation and re-assembly procedure using newer low-cost, mass-produced memory types, such as synchronous DRAM or double data-rate synchronous DRAM (DDR-SDRAM).